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$99

Hardware Description Languages for FPGA Design

Created by -

Timothy Scherr,Benjamin Spriggs
,
University of Colorado Boulder

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English

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Overview

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

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USD 99

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Type: Online

This course includes

  • Approx. 14 hours to complete
  • Earn a Certificate upon completion
  • Start instantly and learn at your own schedule.

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course image

USD 99

provider image

Type: Online

This course includes

  • Approx. 14 hours to complete
  • Earn a Certificate upon completion
  • Start instantly and learn at your own schedule.

Taken this course?

Share your experience with other students

Share

Add Review

Hardware Description Languages for FPGA Design

Created by -

Timothy Scherr,Benjamin Spriggs
,
University of Colorado Boulder

0.00

(0 ratings)

All Levels

Start Date: February 15th 2021

Course Description

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

The information used on this page is how each course is described on the Coursera platform.

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Timothy Scherr,Benjamin Spriggs,University of Colorado Boulder

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